The present invention relates to electronic circuits, and more particularly to offset cancellation for data conversion systems.
In electronics, the circuits do not behave ideally. For example, an ideal amplifier should output no voltage when the input voltage is zero. However, the amplifiers in the real world output some voltages even when the input voltage is zero. That is, the amplifier behaves as if a “voltage” is being input even when the actual input voltage is zero. Such a “phantom input voltage” is commonly referred to as an offset voltage. The voltage output as a result of the offset voltage is referred to as an “offset component” or “offset” herein.
The offset voltage is in part a result of mismatches in differential circuit elements or any asymmetry along the differential path. Mismatches can be attributed to process variations (e.g., differences in device sizes and doping profiles) or signal integrity problems such as parasitic coupling and the like.
FIG. 1 illustrates a circuit 100 including dynamic element matching that is used to remove or reduce the offset by using a chopping technique. The differential signal is “chopped” before it passes through the analog circuitry that adds the offset. Chopping means swapping signals between two terminals or reversing the polarity every clock cycle to give an alternating signal (which appears like a square wave for a constant voltage signal). The chopped signal passes through the analog circuitry, with the offset being added to both the positive and negative portions. After passing through the analog circuitry, the signal is chopped again, to reverse the effect of the original chopping and return the signal to its original polarity. Since the added offset was the same for each clock cycle, the effect is that the signal has a positive offset one clock cycle, then a negative offset the next clock cycle. By then passing through a low pass filter, the offset is removed.
As shown in FIG. 1, circuit 100 includes an input chopper switch 102, an amplifier block 104 (whose offset is to be removed), an output chopper switch 106, and a low-pass filter 108. Input chopper switch 102 receives the input voltage Vin (or input signal) and outputs a first chopped voltage Vx (see FIG. 2A) to amplifier 104 that has an offset voltage Vos associated with it. The voltage passing through the input to analog amplifier block 104 becomes a second voltage Vy that is the sum of Vx and the offset, Vos (see FIG. 2B). The output of amplifier block 104 is an amplified version of the input signal with its offset, signal Vz as shown in FIG. 2C. Output chopper switch 106 receives voltage Vz output by the amplifier 104 and chops it to reverse the original chopping and output a fourth voltage V′out, which is the original signal with the chopping removed and the offset being either positive or negative every other clock cycle. Fourth voltage V′out is passed through low-pass filter 108 to remove the offset component in fourth voltage V′out. The resulting signal is an output voltage Vout (or output signal).
FIGS. 2A-2E illustrate various waveforms associated with dynamic element matching circuit 100. FIG. 2A illustrates first signal Vx that has been chopped-up by the input chopper switch 102. FIG. 2B illustrates second signal Vy with the offset voltage Vos added to the first signal Vx. FIG. 2C illustrates third signal Vz that is output by amplifier 104 after the second signal Vy has been amplified. FIG. 2D illustrates fourth signal V′out output by the output chopper switch 106. FIG. 2E illustrates output signal Vout after the low-pass filter 108 has removed the offset component from fourth signal V′out.